The present invention relates to a technology for designing a semiconductor, and more particularly, to a fuse circuit for performing various circuit operations by using a fuse, and a driving method thereof.
In general, as degree of integration for semiconductor devices including a Double Data Rate Synchronous DRAM (DDR SDRAM) has been rapidly increased, more than tens of millions of memory cells are being provided within one semiconductor device. However, if a failure occurs in any one of these memory cells, a corresponding semiconductor device may fail to perform a desired operation. With technical development of a process of the semiconductor device, a failure occurs in a small amount of memory cells of the semiconductor device. Even if the semiconductor device has few defective memory cells, the semiconductor device may be discarded resulting in poor product yield efficiency. In order to counter this, use of redundancy memory cells also extra normal memory cells have been proposed. If a failure occurs in the normal memory cells, the redundancy memory is replaced and used. Hereafter, a memory cell required to be replaced with a redundancy cell due to presence of defective cells is referred to as “a memory cell to be repaired.”
Address information corresponding to the memory cell to be repaired is programmed in a fuse circuit for redundancy. The fuse circuit for redundancy includes a plurality of fuses for programming of address information. In other words, the fuse circuit for redundancy outputs the programmed address information, and the semiconductor device compares the output signal with address information applied during read and write operations, so that if the memory cell to be repaired is accessed, the redundancy memory cell is allowed to be accessed instead of the memory cell to be repaired.
For reference, a scheme for programming a fuse includes an electrical fuse-cutting method, a laser cutting scheme, or so on. Herein, the electrical fuse-cutting method is based on the fact that over-currents are applied to the fuse to be cut so as to melt, resulting in disconnection of the fuse to be cut. The laser cutting scheme is based on the fact that laser beams are used for blowing of the fuse to be cut, resulting in disconnection of the fuse to be cut. In general, the laser cutting scheme is widely used as compared with the electrical fuse-cutting method, because it is simper than the electrical fuse-cutting method.
Meanwhile, fuses are used in performing various operations throughout semiconductor devices, as well as a fuse circuit for redundancy described above. For example, the fuses are used in tuning a voltage in a constant voltage generation circuit operated sensitively to a process. Also, the fuses are variously used in a control circuit for a test, a control circuit for selection of various modes, or so on. Hereafter, for illustration purpose, a description will be given of an example of a fuse circuit for redundancy that uses fuses.
FIG. 1 is a circuit diagram illustrating a fuse circuit for redundancy, which constitutes a conventional semiconductor device.
Referring to FIG. 1, the fuse circuit for redundancy includes a fuse unit 110, a latching unit 130, a pre-charging unit 150, and a buffering unit 170.
The fuse unit 110 is configured to drive a common node COM of an output stage by a driving current flowing through a current path having a fuse, in response to zero to third fuse enable signals EN_ADD<0:3>. The fuse unit 110 includes a plurality of fuses 112, and a plurality of switching units 114.
The fuses 112 are used to program address information corresponding to a memory cell to be repaired, and include zero to third fuses F0, F1, F2, and F3. The switching units 114 are used to receive the fuse enable signals EN_ADD<0:3>, respectively, so as to form a pull-down current path having a corresponding fuse. The switching units 114 include zero to third NMOS transistors NM0, NM1, NM2, and NM3.
The latching unit 130 is configured to latch a corresponding logic value according to a voltage level of the common node COM operated in response to zero to third fuse enable signals EN_ADD<0:3>. The latching unit 130 includes zero and first inverters INV0, and INV1.
The pre-charging unit 150 is configured to set an initial logic value in the latching unit 130. The pre-charging unit 150 includes a zero PMOS transistor PM0, which has a source-drain path between a power source voltage VDD stage and a common node COM and receives a pre-charging signal PCGB through a gate thereof. Herein, the pre-charging signal PCGB transits from a logic ‘low’ to a logic ‘high’ when a semiconductor device performs an active operation, a read operation, or a write operation.
The buffering unit 170 is configured to receive an output signal of the latching unit 130, and to output a fuse state signal INF_ADD, and includes two inverters. Herein, the fuse state signal INF_ADD includes address information of a memory cell to be repaired programmed in a plurality of the fuses 112. The semiconductor device determines whether a memory cell to be accessed corresponds to a memory cell to be repaired, in response to the fuse state signal INF_ADD.
Hereafter, for illustration purpose, it will be described how the fuse circuit for redundancy is operated according to whether or not a zero fuse enable signal EN_ADD<0> is activated for each of cases where the zero fuse F0 is cut, and not cut.
First, since the common node COM is pre-charged in response to the pre-charging signal PCGB of a logic ‘low’, the latching unit 130 lathes a logic ‘high’. Thereafter, at the time of an active operation, a read operation, or a write operation, the pre-charging signal PCGB transits from a logic ‘low’ to a logic ‘high’, and the zero enable signal EN_ADD<0> is activated to be a logic ‘high’, and thus the zero NMOS transistor NM0 is turned on.
In this case, when the zero fuse F0 is not cut, since a pull-down current path is formed between the common node COM and a ground power source voltage (VSS) stage, a voltage level of the common node COM is lower than a threshold voltage of the zero inverter INV0, and a fuse state signal is a logic ‘high’. Alternatively, when the zero fuse F0 is cut, the common node COM maintains a logic ‘high’ by the latching unit 130. That is, since the pull-up current path by the first driving unit INV1 is made, the common node COM maintains a logic ‘high’, and the fuse state signal INF_ADD is a logic ‘low’.
As described above, the fuse state signal INF_ADD maintains a logic ‘low’ or a logic ‘high’ according to whether or not a corresponding fuse is cut. The semiconductor device receives address information of the memory cell to be repaired based on the fuse state signal INF_ADD.
Meanwhile, as the process technology of the semiconductor device is being advanced, the semiconductor device is being downsized by reduction in spacing not only between components constituting a circuit, but also between fuses. Reduction in spacing between fuses may cause the following problems, when a blowing process is performed for cutting of the fuses.
That is, the fuse adjacent to the fuse to be cut suffers damage (e.g. crack) which is caused by a conductive by-product, and impact generated at the time of performing a blowing process. Of course, the crack may not occur at the time of performing a blowing process, but may occur also due to stress between fuses and insulating layer covering the fuses, or an erroneous process. In case where the crack occurs in the fuse, the most serious problem is that a fuse intended to not be cut may be placed in a situation where the fuse is determined as ‘cut fuse’. This situation may cause a malfunction of the semiconductor device.
In general, the crack occurring in the fuse is classified into three types. The first type is a failure crack that causes failure of the fuse by the crack itself. The second type is a progressive crack that causes failure of a fuse according to an environment and time. The third type is a free crack that does not cause a failure in life time of a semiconductor device because a degree of a crack occurring in the fuse is insignificant. In a case of the first type, since the semiconductor malfunctions before its shipment, its malfunction is detected in a test mode, such as probe test, or a package test, and accordingly, it is possible to prevent its malfunction, or to determine the semiconductor device as a “defective”. However, in a case of the second type, since a malfunction of the semiconductor device is not detected in a test mode performed before its shipment, normal judgment is not made. In addition, because the semiconductor device malfunctions after being shipped, consumers using the semiconductor device may encounter malfunctions.
FIG. 2 is a waveform diagram illustrating a voltage level change of a common node COM according to a fuse stat of FIG. 1.
Referring to FIGS. 1 and 2, when the fuse is cut, the common node COM is driven by a driving current flowing through a pull-up current path made by a first inverter INV1, and maintains a high voltage level. That is, the voltage level of the common node COM is determined by the driving current flowing through the pull-up current path. Alternatively, when the fuse is not cut, the common node COM is driven by the driving current flowing through the pull-down current path which is made by a corresponding fuse and the NMOS transistor coupled to the fuse, and maintains a low voltage level. In this case, a voltage level of the common node COM is determined by a driving current flowing through the pull-up current path and by a driving current flowing through pull-down current path.
FIG. 2 illustrates an example where a voltage level of the common node COM becomes high or low based on a resistance value of a fuse (for example, 60 KΩ). That is, when the resistance value of the fuse is lower than, for example, 60 KΩ, the common node COM has a low voltage level since pre-charged charges are discharged. When the resistance value of the fuse is higher than 60 KΩ, the common node COM maintains a high voltage level by a driving current flowing through the pull-up current path. Then, the voltage level of the common node COM determines a logic level of the fuse state signal INF_ADD. In other words, the logic level of the fuse state signal INF_ADD is determined according to whether or not a fuse is cut.
Meanwhile, a crack may occur in any fuses, as described above. At this time, a resistance value of the fuse not being cut becomes increasingly high according to an environment and time. In other words, a normal fuse in a state of not being cut should have a resistance value lower than, for example, 60 KΩ. If a crack occurs in a fuse, the fuse may have a resistance value higher than that of a fuse where no crack occurs, but the fuse where a crack occurs may have a resistance value lower than 60 KΩ. Therefore, a detection result shows that the fuse where a crack occurs is not cut in a test mode, and thus is determined as a “normal fuse.” However, a resistance value of a fuse where a crack occurs may become higher than 60 KΩ according to an environment and time. At this time, the semiconductor device malfunctions since a fuse not intended to be cut is recognized as a fuse that is cut.
Therefore, the fuse state signal INF_ADD to be a logic ‘high’ for a fuse not intended to be cut is a logic ‘low’ due to the crack, and reliability of the semiconductor device is reduced due to this malfunction.